It is required to adjust a data-width difference between a microprocessor and external memories when a microcomputer system is designed.
We will explain below a conventional data-width adjustment technique which is commonly used in a conventional microprocessor system and a problem included in this conventional technique.
For example, a conventional microprocessor system consists of a microprocessor having 32 bit bus-width, a ROM of 8 bit bus-width for storing a program including instructions, and 4 RAMs, each having 8 bit bus-width, for temporarily storing data.
If the microprocessor has no function for adjusting data-width, as shown in FIG. 1, in order to overcome such drawback there is a conventional method to adjust data-width difference in which the 32 bit data bus 102 of MPU 101 is connected with a 8 bit ROM 103 through a bus-width conversion circuit 104. We will explain below this method and this technique and a problem included in this conventional method.
As shown in FIG. 2, when a microprocessor system does not include the bus-width conversion circuit 104 shown in FIG. 1, there is a method for adjusting the bus-width difference in which the total number of bit-width of ROMs 103 is 32 bits because the total number of the ROMs 103 is four (8 bits.times.4=32 bits). Thus, the 32 bit data bus 102 may be connected directly to the ROMs 102 in the microprocessor system.
In the conventional method shown in FIG. 1, it must be required to add the bus-width conversion circuit 104 in the microprocessor system, on the other hand, the conventional method shown in FIG. 2, the extra three ROMs are further required to the microprocessor system in addition to the ROM 103 in the conventional method shown in FIG. 1. Therefore the configuration of the microprocessor system becomes larger and the cost of the microprocessor system increases.
On the other hand, there is a conventional microprocessor which is capable of fixedly changing the data-width of a data bus based on external signals. In a microprocessor system including such the microprocessor, as shown in FIG. 3, according to the external signal such as 8 bit bus-width indication signal the bus-width of the data bus 105 is set in 8 bits, then four RAMs 106 are connected in parallel to the data bus 105.
However, although the microcomputer system uses these four RAMs 106, the data-width of the ROMs 106 becomes 8 bits in the conventional method described above. In this case, when comparing with the configurations of the microprocessor systems shown in FIGS. 1 and 2, the bit-width of data is decreased, so that the operational performance of the microprocessor system is decreased because the processing function thereof is decreased.
There is a microprocessor having a configuration to overcome the problems described above. This function of the microprocessor is called as "dynamic bus sizing function". In the dynamic bus sizing function, the microprocessor inputs bus-width indication signals per bus cycle in order to repeatedly perform a bus cycle operation for requiring. This function is introduced in many kinds of conventional microprocessors, for example MC68020 manufactured by MOTOROLA corporation.
In this dynamic bus sizing function, the bit-width of external memories to be accessed in each bus cycle is recognized because it must be required to input the bus-width indication signals per bus cycle. For this reason, as shown in FIG. 4, a microprocessor system including a MPU 107 having the dynamic bus sizing function must have a circuit 109 which is generates a bus-width indication signal corresponding to a data-width of an external memory which is recognized for accessing after decoding an address signal transferred to an address bus 108 in the MPU 107.
In the microprocessor system, the bus-width indication signals generated from this circuit 109 is transferred to MPU 107 per bus cycle.
However, in the microprocessor system including the microprocessor 107 having the dynamic bus sizing function, as shown in FIG. 5, the bus-width indication signals are generated by an address driver 112 for transferring address signals output from the MPU 110 to a memory 111, an address decoder 113 for decoding the output from the address driver 112 and then generates a selection signal CS for selecting the memory 111 to be accessed, and a bus-width indication signal generator 114 for generating bus-width indication signals corresponding to the bit-width of the memory to be selected by the selection signal from the address decoder 112.
As shown in a timing chart in FIG. 6, a set-up time to define the following equation. EQU t.sub.cyc -(t.sub.a +t.sub.b +t.sub.c +t.sub.d)&gt;t.sub.e
wherein "t.sub.cyc " is an allowable bus cycle time to access the memory 111, "t.sub.a " is a delay time of address signal output from the MPU 110 in synchronization with a clock signal, "t.sub.b " is a delay time of an address signal by the address driver 112, "t.sub.c " is a delay time of the address decoder 113, "t.sub.d " is a time to be required for generating signals by the generator 114, and "t.sub.e " is a setting up timing of the bus-width indication signal.
Accordingly, as clearly shown in the above equation, the setting-up timing for the bus-width indication signal becomes strict and accessing timing for the memory becomes also rigid when the operational frequency such as the clock signal becomes high in order to reduce the bus cycle time. It causes error operation in the microprocessor system. In addition, in a case where it is required to further reduce the bus cycle time, a high speed operation of the microprocessor system cannot be achieved because the output condition of the bus-width indication signals is not satisfied.
In addition, the microprocessor having a function similar to the dynamic bus sizing function described above is disclosed in the Japanese Patent laid open No.3-98145.
This microprocessor is capable of dynamically changing a bus-width corresponding to the address of a region to be accessed. In this microprocessor signal indicatings a bus-width are generated based on an address decoding result like the microprocessor having the dynamic bus sizing function because a bus-width indication signals is generated after comparing the decoding result of an address signal with a specified address.
Accordingly the same problem is also caused when the microprocessor system in which the decoding operation and the comparing operation are executed because it takes much time to generate bus-width indication signals.
As described above, inconveniences are introduced by using the conventional method for adjusting data-width in a microprocessor system which consists of a microprocessor and external memories which have different data-widths.
Accordingly, this causes memory using efficiency to decrease and the specific configuration to add, so that the configuration and the cost of the microprocessor system become increasing.
When a microprocessor system is constructed by using a microprocessor which is capable of changing temporarily and fixedly a bus-width according to an external signal, a processing function of the microprocessor system is decreased because external memories in the system are not used efficiency. This is also a problem.
On the other hand, when a microprocessor system is constructed by using a microprocessor having the dynamic bus sizing function or a function similar to the dynamic bus sizing function, operational timing of the system is strict, so that a high speed operation becomes difficult. This is also a problem.